The present invention relates to a microprogram-controlled type arithmetic control apparatus utilized in a pipeline processing system.
An advanced approach to improving the speed at which computers can process instructions has been the development of the pipelined processor. These processors can perform many instructions at very high speeds because the internal organization has been designed so as to optimize the number of instructions that can be performed over a period of time. A pipelined processor actually performs certain operations on several different instructions simultaneously. For example, one instruction might call for an operation upon two operands contained within the main memory. These operands might be fetched from main memory during the same period of time that a second instruction was being decoded to determine its type as well as its data requirements. Still a third instruction might be nearing its completion, all in the same machine cycle. Such a pipeline processing unit is disclosed in U.S. Pat. No. 3,771,138 and in U.S. Pat. No. 3,840,861, for example. Therefore, its actual hardward construction is omitted.
At an execution stage of an instruction in a prior art pipeline processing unit, a microinstruction which controls the execution stage is read out of a control memory onto a microinstruction bus. In accordance with the microinstruction, a source data to be input to an arithmetic circuit is read out from a general register, a memory data register or a working register. An arithmetic operation is performed in the arithmetic circuit in accordance with the microinstruction. The result of the arithmetic operation is stored in a general register designated by the microinstruction.
As described above, the execution stage of the instruction necessitates a long processing time from the start to the end of the stage. Thus the processing time for other stages such as a fetch stage, operand address calculation stage and operand read stage should be set in accordance with the execution stage thereby obstructing the improved processing speed of the instruction.